Lithography processes such as photolithography and e-beam lithography utilize resist formulations (e.g., photoresist, e-beam resist). A layer of resist is conventionally applied to a substrate by means of a spin coating process. In accordance with this process, the substrate is secured to a chuck of a coat track apparatus typically using a vacuum. The spin process includes three stages: dispensing the resist solution onto the substrate, accelerating the substrate to a desired rotational speed, and then spinning at a constant speed to establish the desired thickness for the resist. The goal of the deposition process is to apply a uniform, adherent, defect-free layer of resist over the entire substrate. This layer of resist can then be used to form a resist mask. For example, a layer of photoresist can be exposed in a desired pattern using UV radiation directed through a reticle. During a development step, the unexposed resist for a negative tone resist or the exposed resist for a positive tone resist is removed to form the resist mask. In a similar manner, an electron beam resist can be exposed using a focused electron beam and then developed using suitable developers to form a resist mask.
Most spin coating processes are performed at a constant rotational speed of approximately 2000-6000 rpm for 3-30 seconds. A total process time is about 60 seconds. Processes other than spin coating have also been employed to form a layer of resist on a substrate. For example, resist has been extruded in continuous sheet form while the substrate is moved under an extrusion nozzle. Chemical vapor deposition, in which a resist layer is deposited in the presence of a plasma onto the surface of a substrate has also been used. In addition, resist sputtering techniques have been employed. One problem with these alternative methods for forming a layer of resist is that specialized equipment and procedures are required. Moreover, these specialized equipment and processes can be incompatible with equipment and processes conventionally used in volume semiconductor manufacture. For example, standard coat tracks for spinning on resist cannot be used with the above processes.
In the semiconductor industry, silicon structures are constantly being developed which are non-planar. For example, in the manufacture of known good die (KGD), test carriers are used for testing and burning-in the dice. These test fixtures typically include an electrical interconnect adapted to establish a temporary electrical connection with the die. U.S. Pat. No. 5,408,190 to Wood et al. describes such a test fixture.
The interconnects for these test fixtures can include a substrate formed of a material such as silicon. Raised projections can be formed integrally with the substrate in a pattern that matches the size and spacing of the bond pads on the dice. The raised projections and a conductive layer deposited on the projections form contact members for contacting the bond pads on the die to form the temporary electrical connection. The height of each projection, as measured from the top of the substrate to the tip of the projection, can vary from a few angstroms to about 100 .mu.m. In a subsequent lithographic process, it is difficult to apply resist to the substrate using a spin coating process because the resist coats unevenly on the raised topography. In particular, voids are formed in some areas, such as between the projections, and these areas do not uniformly coat with resist. The sidewalls of the projections are also difficult to coat with resist because the resist tends to slide off of the sidewalls. This results in almost no resist coverage on the sidewalls.
Another example of a non-planar topography that is difficult to uniformly coat with a layer of resist occurs in the manufacture of DRAMs. In some cases metallization interconnect layers must be formed on substrates having a non-planar topography. For example, an uneven or non-planar topography can be caused by the formation and stacking of various semiconductor devices beneath the interconnect layers. By way of example, U.S. Pat. No. 5,354,705 to Mathews et al., discloses a method for forming semiconductor structures having a non-planar topography. Coating resist on this type of non-planar topography using conventional techniques, such as spin coating, can lead to voids and non-uniform coverage.
Other silicon structures can also have non-planar topographies and projecting structures of varying height. When it is necessary to apply resist to these raised, non-planar topographies, the conventional application methods as described above provide poor results. In particular a conformal, void free layer of resist cannot be applied with a uniform thickness and does not adequately cover the sidewalls of various projecting structures or plateaus.